Semiconductor Silicon — EG Wafer Supply Chain
title: "Semiconductor Silicon — EG Wafer Supply Chain" description: "Electronic-grade silicon, Czochralski and float-zone crystal growth, CMP slurry with fumed silica, and the wafer supply chain to chip fabs." section: "downstream"
Electronic-Grade Silicon
Semiconductor wafers require silicon of extraordinary purity: electronic-grade (EG) polysilicon at 9N–11N (99.9999999%–99.999999999%), roughly 1000× purer than solar-grade material. Metallic impurities above a few parts-per-trillion can degrade carrier lifetime and kill device yield.
Starting from metallurgical silicon, EG polysilicon is produced by the Siemens process: trichlorosilane (TCS) is purified by fractional distillation and then thermally decomposed on hot silicon rods to deposit high-purity silicon. The resulting chunky polysilicon rods are broken, loaded into a Czochralski (CZ) puller, and melted in a quartz crucible.
Crystal Growth and Wafering
In CZ growth, a seed crystal contacts the melt surface and is slowly withdrawn while rotating, pulling a cylindrical ingot. Precise temperature control and pull rate determine oxygen content, resistivity, and crystal defect density.
Float-zone (FZ) purification — passing a molten zone along a rod — yields even lower impurity levels (≤1 ppb total metals) for power devices and detectors.
| Method | Diameter | Oxygen content | Typical use |
|---|---|---|---|
| CZ | 200–300 mm | 5–15 ppma | Logic, memory, RF |
| FZ | 100–200 mm | <0.1 ppma | Power devices, detectors |
| MCZ | 300 mm | Controlled | Advanced logic nodes |
After growth, ingots are ground, sliced with diamond wire saws, and polished through multiple lapping and CMP steps to achieve sub-nanometre surface roughness.
CMP and Fumed Silica
Chemical-mechanical planarisation (CMP) is the most silicon-chemistry-intensive step in wafer finishing. Silica-based CMP slurries — colloidal silica or fumed silica particles dispersed in alkaline chemistry — remove surface defects and achieve the mirror finish required by lithography tools.
Fumed silica with controlled particle size distribution (primary particle 7–40 nm) is a key abrasive component in both wafer polishing and interlayer dielectric (ILD) planarisation inside the fab.